About the internships:

The Jožef Stefan Institute (Department K5) offers internship opportunities under the supervision of Prof. dr. Hana Uršič Nemevšek, focusing on advanced materials and semiconductor-related technologies.

Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates.

Internship topics:

1. Deposition and properties of electrodes on silicon substrates
2. Deposition and functional properties of various dielectric layers on
   silicon substrates
3. Study of topography and local functional properties layers on silicon substrates
4. Study of microstructure of functional layers on silicon substrates
5. Multilayer structures on silicon substrates

Kje:

Jožef Stefan Institute (IJS), Jamova 39, Ljubljana, Slovenia

Duration:

1–3 months (approx. 100 hours/month)

Rok za prijavo:

applications accepted on ongoing basis

Contact:

Prof. dr. Hana Uršič Nemevšek (Department K5)

E-mail: Hana.ursic@ijs.si

Additional internship opportunities at IJS

ASIC Design and Verification

Mentor: Jure Vreča
Available positions: 3

1. ASIC design with open-source tools – tapeout possibility
2. ASIC verification

Contact:
Jure Vreča

E-mail: jure.vreca@ijs.si

Digital Circuit Design and Verification using SystemVerilog

Mentor: Rok Žitko
Available positions: 3

1. Training in the use of tools for the development and verification of digital circuits in SystemVerilog for further development of the PulsePins control system.
   Project link:
   https://github.com/rokzitko/PulsePins
2. Training in the use of tools for the development and verification of digital circuits in SystemVerilog for random number generators based on vacuum fluctuations and real-time entropy extraction.
   Project link:
   https://github.com/rokzitko/toeplitz

Contact:
Rok Žitko

E-mail: rok.zitko@ijs.si

Silicon Device Simulations using COMSOL

Mentor: Uroš Cvelbar
Available positions: 1

1. Different topics on simulations of silicon devices using COMSOL software

Contact:
Uroš Cvelbar

E-mail: uros.cvelbar@ijs.si

Semiconductor Processing and Electronics Applications

Mentor: Žiga Brenčič
Available positions: 3
Internship duration: 1–3 months

1. Ion implantation for chip production
2. Electronics for space applications
3. Electronics for nuclear applications

Contact:
Žiga Brenčič

E-mail: ziga.brencic@ijs.si

Applications

Applications are accepted on an ongoing basis.
Candidates should contact the mentor directly to discuss their background, interests, and internship availability.