Available internships:
Advanced materials and semiconductor-related technologies
The Jožef Stefan Institute (Department K5) offers internship opportunities under the supervision of Prof. dr. Hana Uršič Nemevšek , focusing on advanced materials and semiconductor-related technologies.
Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates.
Internship topics:
- Deposition and properties of electrodes on silicon substrates
- Deposition and functional properties of various dielectric layers on
silicon substrates - Study of topography and local functional properties layers on silicon substrates
- Study of microstructure of functional layers on silicon substrates
- Multilayer structures on silicon substrates
- Provider: CC Chip.si in collaboration with JSI
- Duration: 1–3 months (approx. 100 hours/month)
- Rok za prijavo: applications accepted on ongoing basis
- Location: Jožef Stefan Institute (IJS), Jamova 39, Ljubljana, Slovenia
- Contact: Prof. dr. Hana Uršič Nemevšek (Department K5), E-mail: Hana.ursic@ijs.si
ASIC Deaign and Verification
Internship topics:
- ASIC design with open-source tools – tapeout possibility
- ASIC verification
- Provider: CC Chip.si in collaboration with JSI
- Mentor: Jure Vreča
- Available positions: 3
- Contact: Jure Vreča, E-mail: jure.vreca@ijs.si
Digital Circuit Design and Verification using SystemVerilog
Internship topics:
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Training in the use of tools for the development and verification of digital circuits in SystemVerilog for further development of the PulsePins control system.
Project link:
https://github.com/rokzitko/PulsePins - Training in the use of tools for the development and verification of digital circuits in SystemVerilog for random number generators based on vacuum fluctuations and real-time entropy extraction.
Project link:
https://github.com/rokzitko/toeplitz
- Provider: CC Chip.si in collaboration with JSI
- Mentor: Rok Žitko
- Available positions: 3
- Contact: Rok Žitko, E-mail: rok.zitko@ijs.si
Silicon Devices Simulations using COMSOL
Internship topics:
- Different topics on simulations of silicon devices using COMSOL software
- Provider: CC Chip.si in collaboration with JSI
- Mentor: Uroš Cvelbar
- Available positions: 1
- Contact: Uroš Cvelbar, E-mail: uros.cvelbar@ijs.si
Semiconductor Processing and Electronics Applications
Internship topics:
- Ion implantation for chip production
- Electronics for space applications
- Electronics for nuclear applications
- Mentor: Žiga Brenčič
- Available positions: 3
- Internship duration: 1–3 months
- Kontakt: Žiga Brenčič, E-mail: ziga.brencic@ijs.si
Additional information
Applications
Applications are accepted on an ongoing basis.
Candidates should contact the mentor directly to discuss their background, interests, and internship availability.
