About the training:
The 3-day (24-hour) course will introduce high-level digital circuit synthesis (HLS) and optimization from algorithms in the C/C++ language. It covers digital design description in programming languages, hardware-specific libraries, and design techniques. The AMD Vitis HLS development tool and AMD (Xilinx) development boards will be used for practical experiments.
Participants will gain hands-on experience with FPGA-based development workflows and practical implementation on AMD (Xilinx) platforms.
Who Should Attend?
Developers of digital electronic systems from companies and research organizations and other participants who want to acquire fundamental knowledge in the field of high-level digital circuit design with FPGA building blocks.
Kdaj:
1–3 June 2026
Kje:
Faculty of Electrical Engineering, University of Ljubljana (UL FE), Tržaška cesta 25, Ljubljana
Topics:
- Fundamentals of High-Level Synthesis (HLS) and FPGA systems
- AMD Vitis HLS and Vivado design tools
- Digital component design and synthesis
- Implementation on the RedPitaya platform
- FIR filter and AXI interface design
- Integration of FPGA-based processing chains
Overview of the Programme (detailed program will be published soon)
The training will include lectures and hands-on laboratory sessions.
Day 1 – Introduction to High-Level Synthesis (HLS)
- Introduction to FPGA SoC systems and RTL design limitations
- Overview of AMD Vitis HLS and Vivado workflows
- Synthesizable C++, data types, directives, and optimization techniques
- Fixed-point arithmetic and quantization concepts
- Hands-on laboratory session on simulation, synthesis, and filter design
Day 2 – HLS IP Design for RedPitaya
- Introduction to the RedPitaya architecture and interfaces
- HLS IP synthesis for signal-processing applications
- FIR filter design and implementation
- Integration and testing of FPGA components on RedPitaya
- Practical laboratories and individual design exercises
Day 3 – System-Level Integration
- AXI interfaces and HLS directives for hardware accelerators
- Matrix multiplication and FPGA-based signal-processing systems
- Design and implementation of custom IP cores
- Dataflow pipelines and multi-stage processing chains
- Final hands-on integration and testing on RedPitaya
- Knowledge evaluation for certification
Learning Outcomes
After successful completion of the course participants will:
- understand the concept of HLS and the limitations of the RTL approach
- know how to use Vitis HLS and Vivado for simulation, synthesis and basic optimization of C/C++ functions,
- be able to analyze synthesis results and evaluate the impact of directives and data types,
- know how to implement synthesized components on FPGA platforms,
- have experiences in design and synthesizes own hardware signal processing components to know how to read to the requirements of the data flow.
Additional Information:
Cost: Udeležba je brezplačna
Accreditation and Microcredential
This training is accredited with a microcredential. Participants who successfully complete the course will receive a microcredential worth 1 ECTS credit
Organizer:
CC-Chip.si in collaboration with Laboratory for integrated circuit design, UL FE
About us: The laboratory members have decades of experience in developing digital circuits with FPGA building blocks, teaching and mentoring students at all levels of study, and conducting educational courses for industrial partners.
Registracija:
Registrations for this course are full.
If you are interested in a future course session, please contact us at office@cc-chip.si. If there is sufficient interest, an additional course session will be organised in September.
Contact:
E-mail: office@cc-chip.si
