About the training:
This 5-day course will familiarize participants with real world design problems of integrated circuits. The goal of a workshop is to design a custom analog integrated circuit which works at different process, voltage and temperature (PVT) variations. This includes a custom design of analog circuit schematic, determining appropriate values for components and drawing a layout that can be send to fabrication.
Who Should Attend?
Participants should have knowledge of Cadence Virtuoso EDA including cell hierarchy, schematic design, adexl simulations, test creation for simulations (tran, ac, dc sweep, Monte Carlo), corner analysis and basic layout knowledge (layer definitions, DRC, LVS, parasitic extraction).
The training is open to all interested participants with a relevant technical background.
Kdaj:
6 – 10 July 2026
Kje:
Faculty of Electrical Engineering, University of Ljubljana (UL FE), Tržaška cesta 25, Ljubljana
Topics:
- ASIC design
- Analog integrated circuits
- Cadence Virtuoso EDA
- Process, voltage and temperature (PVT) variations
- Design constraints
- Schematic design
- Layout design
Additional Information:
Cost: Udeležba je brezplačna
Organizer:
CC-Chip.si, Žiga Šmelcer from The Laboratory of Microelectronics (LMFE), UL FE
Registracija:
Registrations will open soon
Note that registrations are limited to ensure an interactive and hands-on learning experience.
Note!: By attending the workshop you are agreeing that you will sign and act according to non-disclosure agreement from technology provider. This means that technology definitions are confidential information and you will not share or transfer information from our servers. The signature makes you liable in case of disclosure of any NDA-protected information
Contact:
E-mail: office@cc-chip.si
