Following the successful training in June 2026, we offer a repetition of the three-day hands-on training from 20 to 22 January 2027.
About the Training:
The course will introduce high-level digital circuit synthesis (HLS) and optimization from algorithms in the C/C++ language. It covers digital design description in programming languages, hardware-specific libraries, and design techniques. The AMD Vitis HLS development tool and AMD (Xilinx) development boards will be used for practical experiments.
Participants will gain hands-on experience with FPGA-based development workflows and practical implementation on AMD (Xilinx) platforms.
Participants who successfully complete the training will receive a micro-credential issued by the University of Ljubljana.
Topics:
- Fundamentals of High-Level Synthesis (HLS) and FPGA systems
- AMD Vitis HLS and Vivado design tools
- Digital component design and synthesis
- Implementation on the RedPitaya platform
- FIR filter and AXI interface design
- Integration of FPGA-based processing chains
Overview of the Programme
Day 1 – Introduction to High-Level Synthesis (HLS)
- Introduction to FPGA SoC systems and RTL design limitations
- Overview of AMD Vitis HLS and Vivado workflows
- Synthesizable C++, data types, directives, and optimization techniques
- Fixed-point arithmetic and quantization concepts
- Hands-on laboratory session on simulation, synthesis, and filter design
Day 2 – HLS IP Design for RedPitaya
- Introduction to the RedPitaya architecture and interfaces
- HLS IP synthesis for signal-processing applications
- FIR filter design and implementation
- Integration and testing of FPGA components on RedPitaya
- Practical laboratories and individual design exercises
Day 3 – System-Level Integration
- AXI interfaces and HLS directives for hardware accelerators
- Matrix multiplication and FPGA-based signal-processing systems
- Design and implementation of custom IP cores
- Dataflow pipelines and multi-stage processing chains
- Final hands-on integration and testing on RedPitaya
Learning Outcomes
- understands the concept of HLS and the limitations of the RTL approach,
- use Vitis HLS and Vivado for simulation, synthesis and basic optimization of C/C++ functions,
- analyze synthesis results and evaluate the impact of directives and data types,
- implement synthesized components on FPGA platforms
- design and synthesizes own hardware signal processing components tailored to the requirements of the data flow.
Who Should Attend?
Developers of digital electronic systems and other participants who want to acquire fundamental knowledge in the field of high-level digital circuit design with FPGA building blocks.
Key Information:
Where: Fakulteta za elektrotehniko, Univerza v Ljubljani
When: 20 – 22 January 2027
Organizer: Faculty of Electrical Engineering, University of Ljubljana
Cost: Free of charge
Registration: Required – please register by 11 january 2027
Contact:
For additional information, please contact the CC Chip.si main office
E-mail: office@cc-chip.si
