About the training:

A hands-on, bare-metal course on the SiFive FE310-G002 RISC-V microcontroller (HiFive1 board), centered on interrupts, the machine timer, and, as its core, building a preemptive round-robin task scheduler with full context switching. Participants implement the scheduler from the ground up, programming mostly in C and using a small amount of RISC-V assembly only where it is genuinely required.

Who Should Attend?

Students, PhD candidates, researchers, and engineers with a working knowledge of C who want to understand how interrupts, the machine timer, and a preemptive task scheduler work at the hardware level on RISC-V.

Prerequisites:

• A working knowledge of the C programming language (variables, functions, pointers, structs, and bitwise operators).
• Basic assembly programming skills — familiarity with registers, instructions, and the load/store model (prior RISC-V experience is helpful but not required; the relevant RISC-V instructions are introduced as needed).
• Basic familiarity with how a microcontroller works (memory, registers, and peripherals) at an introductory level.

When:

30.6, 1.7. and 2.7.2026

Approximate start and end time: 10:00-15:00

Where:

Faculty of Computer and Information Science(UL FRI), 100 Ljubljana, Večna pot 113, PR09

Topics:

• The machine timer as the heart of the course: the FE310 CLINT, the mtime / mtimecmp registers, and how a periodic timer interrupt drives the whole system.
• RISC-V interrupts and exceptions: privileged modes and the machine-mode control and status registers (mstatus, mie, mip, mcause, mtvec).
• Interrupt entry and exit: what the hardware saves automatically, what the handler must save, and the mret return mechanism.
• Building an interrupt vector table and writing timer interrupt handlers — primarily in C, dropping into a small amount of RISC-V assembly only where unavoidable (CSR access and the context switch).
• Register-level context switching: saving and restoring a task’s complete state across a timer interrupt.
• Core of the course — a preemptive round-robin task scheduler with full context switching, built step by step on the machine timer interrupt (task control blocks, stack-frame initialisation, time slices, and starting the scheduler via an environment call).
• Global interrupts and the Platform-Level Interrupt Controller (PLIC): priorities, enabling sources, and the claim/complete handshake for peripheral interrupts.
• Supporting material (kept brief, for a visible result): memory-mapped I/O and a minimal GPIO/UART driver, used only to produce visual/serial output from the running tasks.

Overview of the Programme (detailed program will be published soon)

This hands-on course teaches preemptive multitasking on the SiFive FE310-G002 RISC-V microcontroller (the chip on the HiFive1 board), built from the ground up on interrupts and the machine timer. The central goal is for participants to implement, and fully understand, a preemptive round-robin task scheduler with complete context switching. To get there, the course develops the RISC-V interrupt and exception model: privileged modes, the machine-mode control and status registers, how the CPU enters and leaves a trap, and how to write timer interrupt handlers. Building on this, participants implement a register-level context switch and assemble it into a working scheduler in which several tasks share the CPU under timer-driven preemption. The course also covers external/peripheral interrupts through the Platform-Level Interrupt Controller (PLIC). The course is taught mostly in C — used for the drivers, handlers, and the scheduler itself — while a small amount of RISC-V assembly is introduced only where it is genuinely required, namely accessing the machine-mode CSRs and performing the context switch. Memory-mapped I/O and a minimal GPIO/UART driver are treated only briefly, just enough to produce a visible output (a blinking LED or serial messages) from the scheduled tasks. Every concept is backed by complete, runnable C and assembly code, an online book, and a full source repository. The course suits students and engineers with a working knowledge of C; prior assembly experience is helpful but not required.

Learning Outcomes

After successful completion of the course participants will:

• Explain the RISC-V privileged-mode model and the role of the machine-mode CSRs in handling interrupts and exceptions.
• Describe precisely what the hardware does on interrupt entry and exit, and the function of the mret instruction.
• Configure the machine timer (CLINT mtime / mtimecmp) to generate periodic interrupts and drive preemption at fixed time slices.
• Set up the trap vector table and write correct timer interrupt handlers, working mainly in C and using RISC-V assembly only where required.
• Implement a register-level context switch in assembly that saves and restores a task’s complete state.
• Design and implement a preemptive round-robin task scheduler with full context switching, including task control blocks, stack-frame initialisation, and starting the scheduler.
• Configure the PLIC (priorities, source enables, and the claim/complete handshake) to service peripheral interrupts.
• Work primarily in C for bare-metal development, and read and write the small amount of RISC-V assembly needed for CSR access and context switching.

Additional Information:

Cost: Free of charge

Organizer:

CC-Chip.si in collaboration with prof. dr. Patricio Bulić from Faculty of Computer and Information Science

Registration:

Registration is limited to maintain a small group size and provide each participant with access to dedicated computers and laboratory equipment.

Contact:

For all additional infomration please contact CC Chip.si main office.

E-mail: office@cc-chip.si