{"id":35475,"date":"2026-06-11T10:15:26","date_gmt":"2026-05-01T10:01:55","guid":{"rendered":"https:\/\/cc-chip.si\/?p=508"},"modified":"2026-07-28T08:01:01","modified_gmt":"2026-07-28T08:01:01","slug":"bare-metal-programming-on-risc-v","status":"publish","type":"post","link":"https:\/\/cc-chip.si\/slo\/bare-metal-programming-on-risc-v\/","title":{"rendered":"Bare Metal Programming on RISC-V"},"content":{"rendered":"<h5 class=\"wp-block-heading\"><strong>About the training:<\/strong><\/h5>\n\n\n\n<p class=\"wp-block-paragraph\">A hands-on, bare-metal course on the SiFive FE310-G002 RISC-V microcontroller (HiFive1 board), centered on interrupts, the machine timer, and, as its core, building a preemptive round-robin task scheduler with full context switching. Participants implement the scheduler from the ground up, programming mostly in C and using a small amount of RISC-V assembly only where it is genuinely required.<\/p>\n\n\n\n<h5 class=\"wp-block-heading\"><strong>Prerequisites:<\/strong><\/h5>\n\n\n\n<ul class=\"wp-block-list\">\n<li>A working knowledge of the C programming language (variables, functions, pointers, structs, and bitwise operators).<\/li>\n\n\n\n<li>Basic assembly programming skills \u2014 familiarity with registers, instructions, and the load\/store model (prior RISC-V experience is helpful but not required; the relevant RISC-V instructions are introduced as needed).<\/li>\n\n\n\n<li>Basic familiarity with how a microcontroller works (memory, registers, and peripherals) at an introductory level.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>When:<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">30.6.2026 &#8211; 2.7.2026<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Approximate start and end time: <\/strong>10:00-15:00<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Where:<\/strong> <\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Faculty of Computer and Information Science(UL FRI), 100 Ljubljana, Ve\u010dna pot 113, PR09<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h5 class=\"wp-block-heading\"><strong>Topics:<\/strong><\/h5>\n\n\n\n<ul class=\"wp-block-list\">\n<li>The machine timer as the heart of the course: the FE310 CLINT, the mtime \/ mtimecmp registers, and how a periodic timer interrupt drives the whole system.<\/li>\n\n\n\n<li>RISC-V interrupts and exceptions: privileged modes and the machine-mode control and status registers (mstatus, mie, mip, mcause, mtvec).<\/li>\n\n\n\n<li>Interrupt entry and exit: what the hardware saves automatically, what the handler must save, and the mret return mechanism.<\/li>\n\n\n\n<li>Building an interrupt vector table and writing timer interrupt handlers \u2014 primarily in C, dropping into a small amount of RISC-V assembly only where unavoidable (CSR access and the context switch).<\/li>\n\n\n\n<li>Register-level context switching: saving and restoring a task\u2019s complete state across a timer interrupt.<\/li>\n\n\n\n<li>Core of the course \u2014 a preemptive round-robin task scheduler with full context switching, built step by step on the machine timer interrupt (task control blocks, stack-frame initialisation, time slices, and starting the scheduler via an environment call).<\/li>\n\n\n\n<li>Global interrupts and the Platform-Level Interrupt Controller (PLIC): priorities, enabling sources, and the claim\/complete handshake for peripheral interrupts.<\/li>\n\n\n\n<li>Supporting material (kept brief, for a visible result): memory-mapped I\/O and a minimal GPIO\/UART driver, used only to produce visual\/serial output from the running tasks.<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h5 class=\"wp-block-heading\"><strong>Overview of the Programme (detailed program will be published soon)<\/strong><\/h5>\n\n\n\n<p class=\"wp-block-paragraph\">This hands-on course teaches preemptive multitasking on the SiFive FE310-G002 RISC-V microcontroller (the chip on the HiFive1 board), built from the ground up on interrupts and the machine timer. The central goal is for participants to implement, and fully understand, a preemptive round-robin task scheduler with complete context switching. To get there, the course develops the RISC-V interrupt and exception model: privileged modes, the machine-mode control and status registers, how the CPU enters and leaves a trap, and how to write timer interrupt handlers. Building on this, participants implement a register-level context switch and assemble it into a working scheduler in which several tasks share the CPU under timer-driven preemption. The course also covers external\/peripheral interrupts through the Platform-Level Interrupt Controller (PLIC). The course is taught mostly in C \u2014 used for the drivers, handlers, and the scheduler itself \u2014 while a small amount of RISC-V assembly is introduced only where it is genuinely required, namely accessing the machine-mode CSRs and performing the context switch. Memory-mapped I\/O and a minimal GPIO\/UART driver are treated only briefly, just enough to produce a visible output (a blinking LED or serial messages) from the scheduled tasks. Every concept is backed by complete, runnable C and assembly code, an online book, and a full source repository. The course suits students and engineers with a working knowledge of C; prior assembly experience is helpful but not required.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h5 class=\"wp-block-heading\"><strong>Learning Outcomes<\/strong><\/h5>\n\n\n\n<p class=\"wp-block-paragraph\">After successful completion of the course participants will:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Explain the RISC-V privileged-mode model and the role of the machine-mode CSRs in handling interrupts and exceptions.<\/li>\n\n\n\n<li>Describe precisely what the hardware does on interrupt entry and exit, and the function of the mret instruction.<\/li>\n\n\n\n<li>Configure the machine timer (CLINT mtime \/ mtimecmp) to generate periodic interrupts and drive preemption at fixed time slices.<\/li>\n\n\n\n<li>Set up the trap vector table and write correct timer interrupt handlers, working mainly in C and using RISC-V assembly only where required.<\/li>\n\n\n\n<li>Implement a register-level context switch in assembly that saves and restores a task\u2019s complete state.<\/li>\n\n\n\n<li>Design and implement a preemptive round-robin task scheduler with full context switching, including task control blocks, stack-frame initialisation, and starting the scheduler.<\/li>\n\n\n\n<li>Configure the PLIC (priorities, source enables, and the claim\/complete handshake) to service peripheral interrupts.<\/li>\n\n\n\n<li>Work primarily in C for bare-metal development, and read and write the small amount of RISC-V assembly needed for CSR access and context switching.<a id=\"_msocom_1\"><\/a><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h5 class=\"wp-block-heading\"><strong>Additional Information:<\/strong><\/h5>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Cost: <\/strong>Free of charge<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Organizer:<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">CC-Chip.si in collaboration with prof. dr. Patricio Buli\u0107 from Faculty of Computer and Information Science<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Registration:<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Registration is limited to maintain a small group size and provide each participant with access to dedicated computers and laboratory equipment.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Contact:<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">For all additional infomration please contact CC Chip.si main office.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">E-mail: <a href=\"mailto:Hana.ursic@ijs.si\" target=\"_blank\" rel=\"noopener\" title=\"mailto:office@cc-chip.si\">office@cc-chip.si<\/a><\/p>\n\n\n\n<figure class=\"wp-block-gallery has-nested-images columns-default is-cropped wp-block-gallery-1 is-layout-flex wp-block-gallery-is-layout-flex\">\n<figure class=\"wp-block-image size-large\"><img fetchpriority=\"high\" decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35571\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-1024x684.jpg\" alt=\"\" class=\"wp-image-35571\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05545-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35572\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-1024x684.jpg\" alt=\"\" class=\"wp-image-35572\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05546-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35573\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-1024x684.jpg\" alt=\"\" class=\"wp-image-35573\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05547-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35574\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-1024x684.jpg\" alt=\"\" class=\"wp-image-35574\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05548-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35575\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-1024x684.jpg\" alt=\"\" class=\"wp-image-35575\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05549-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35576\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-1024x684.jpg\" alt=\"\" class=\"wp-image-35576\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05550-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"684\" data-id=\"35577\" src=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-1024x684.jpg\" alt=\"\" class=\"wp-image-35577\" srcset=\"https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-1024x684.jpg 1024w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-300x200.jpg 300w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-768x513.jpg 768w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-1536x1026.jpg 1536w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-2048x1368.jpg 2048w, https:\/\/cc-chip.si\/wp-content\/uploads\/2026\/06\/DSC05554-18x12.jpg 18w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>","protected":false},"excerpt":{"rendered":"<p>About the training: A hands-on, bare-metal course on the SiFive FE310-G002 RISC-V microcontroller (HiFive1 board), centered on interrupts, the machine timer, and, as its core, building a preemptive round-robin task scheduler with full context switching. Participants implement the scheduler from the ground up, programming mostly in C and using a small amount of RISC-V assembly [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":35484,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,14,8],"tags":[13],"class_list":["post-35475","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-cc-chip-si-trainings","category-news","category-trainings","tag-past"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35475","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/comments?post=35475"}],"version-history":[{"count":5,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35475\/revisions"}],"predecessor-version":[{"id":35578,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35475\/revisions\/35578"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media\/35484"}],"wp:attachment":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media?parent=35475"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/categories?post=35475"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/tags?post=35475"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}