{"id":35352,"date":"2026-05-04T08:10:19","date_gmt":"2026-05-04T08:10:19","guid":{"rendered":"https:\/\/cc-chip.si\/?p=508"},"modified":"2026-09-25T10:05:54","modified_gmt":"2026-09-25T10:05:54","slug":"asic-design-summer-school","status":"publish","type":"post","link":"https:\/\/cc-chip.si\/slo\/asic-design-summer-school\/","title":{"rendered":"Te\u010daj ASIC Design"},"content":{"rendered":"
About the training:<\/strong><\/h5>\n\n\n\n

This 5-day course will familiarize participants with real world design problems of integrated circuits. The goal of a workshop is to design a custom analog integrated circuit which works at different process, voltage and temperature (PVT) variations. This includes a custom design of analog circuit schematic, determining appropriate values for components and drawing a layout that can be send to fabrication.<\/p>\n\n\n\n

Who Should Attend?<\/strong><\/h5>\n\n\n\n

Participants are expected to have knowledge of Cadence Virtuoso EDA including cell hierarchy, schematic design, adexl simulations, test creation for simulations (tran, ac, dc sweep, Monte Carlo), corner analysis and basic layout knowledge (layer definitions, DRC, LVS, parasitic extraction).<\/p>\n\n\n\n

The training is open to experts from companies and all other interested with a relevant technical background.<\/p>\n\n\n\n

When:<\/strong><\/p>\n\n\n\n

6 \u2013 10 July 2026<\/p>\n\n\n\n

Where:<\/strong> <\/p>\n\n\n\n

Faculty of Electrical Engineering, University of Ljubljana (UL FE), Tr\u017ea\u0161ka cesta 25, Ljubljana<\/p>\n\n\n\n

<\/p>\n\n\n\n

Topics:<\/strong><\/h5>\n\n\n\n