{"id":35254,"date":"2026-09-02T10:01:55","date_gmt":"2026-09-02T10:01:55","guid":{"rendered":"https:\/\/cc-chip.si\/?p=508"},"modified":"2026-10-29T09:48:43","modified_gmt":"2026-10-29T09:48:43","slug":"high-level-fpga-design-training","status":"publish","type":"post","link":"https:\/\/cc-chip.si\/slo\/high-level-fpga-design-training\/","title":{"rendered":"FPGAs for High Performance Computing"},"content":{"rendered":"
Ve\u010d o izobra\u017eevanju:<\/strong><\/h5>\n\n\n\n

This workshop is jointly organized by the Competence Centre for Chips (Chips.si<\/a>) and the Competence Centre for High-Performance Computing (Sling.si<\/a>). On the workshop, we introduce the fundamentals of HPC technologies, covering computing architectures, parallelism, and the role of hardware accelerators in modern supercomputing, and then explore how FPGAs are programmed in an HPC context through the high-level synthesis (HLS) design flow. HLS allows application-specific accelerators to be described, debugged, and implemented on FPGAs using C\/C++ rather than hardware description languages such as VHDL or Verilog. Through simple examples, participants will learn how to write synthesizable kernels, transfer data between the host and an FPGA board, and apply optimization techniques to improve speed and resource utilization. As a case study, we will develop an accelerator for Cholesky matrix decomposition using C\/C++ together with the OpenCL and XRT libraries on AMD-Xilinx FPGAs. While the sessions primarily target AMD-Xilinx boards, the principles gained apply just as well to FPGAs from other vendors. <\/p>\n\n\n\n

Who Should Attend?<\/strong><\/h5>\n\n\n\n

Everyone is eligible to attend the workshop. No specific requirments.<\/p>\n\n\n\n

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Language: <\/h5>\n\n\n\n

English<\/p>\n\n\n\n

When:<\/strong><\/p>\n\n\n\n

4 \u2013 5 November 2026<\/p>\n\n\n\n

Where:<\/strong> <\/p>\n\n\n\n

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Online: The link will be provided after registration<\/p>\n\n\n\n

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Topics:<\/strong><\/h5>\n\n\n\n