{"id":35093,"date":"2026-05-05T10:44:55","date_gmt":"2026-01-20T17:36:53","guid":{"rendered":"https:\/\/cc-chip.si\/?p=508"},"modified":"2026-08-06T09:01:14","modified_gmt":"2026-08-06T09:01:14","slug":"open-internship-positions-at-institut-jozef-stefan-ijs","status":"publish","type":"post","link":"https:\/\/cc-chip.si\/slo\/open-internship-positions-at-institut-jozef-stefan-ijs\/","title":{"rendered":"Open Internship positions at Institut &#8220;Jozef Stefan&#8221; (IJS)"},"content":{"rendered":"<p class=\"wp-block-paragraph\"><strong>Available internships:<\/strong><\/p>\n\n\n\n<div class=\"wp-block-group is-layout-constrained wp-block-group-is-layout-constrained\">\n<h2 class=\"wp-block-heading has-text-color has-link-color wp-elements-1\" style=\"color:#004180\"><strong>Advanced materials and semiconductor-related technologies<\/strong><\/h2>\n\n\n\n<div class=\"wp-block-group is-layout-constrained wp-block-group-is-layout-constrained\">\n<div class=\"wp-block-group is-layout-constrained wp-block-group-is-layout-constrained\">\n<p class=\"has-medium-font-size wp-block-paragraph\">The Jo\u017eef Stefan Institute (Department K5) offers internship opportunities under the supervision of <strong>\n<a href=\"https:\/\/www-k5.ijs.si\/en\/researchers\/prof-dr-hana-ursic-nemevsek\/\" style=\"color:#0056B3;\" target=\"_blank\" rel=\"noopener\" title=\"\">\nProf. dr. Hana Ur\u0161i\u010d Nemev\u0161ek\n<\/a>\n<\/strong>, focusing on advanced materials and semiconductor-related technologies.<\/p>\n\n\n\n<p class=\"has-medium-font-size wp-block-paragraph\">Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n<\/div>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Internship topics<\/strong>:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Deposition and properties of electrodes on silicon substrates<\/li>\n\n\n\n<li>Deposition and functional properties of various dielectric layers on<br>silicon substrates<\/li>\n\n\n\n<li>Study of topography and local functional properties layers on silicon substrates<\/li>\n\n\n\n<li>Study of microstructure of functional layers on silicon substrates<\/li>\n\n\n\n<li>Multilayer structures on silicon substrates<\/li>\n<\/ol>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Provider:<\/strong> CC Chip.si in collaboration with JSI<\/li>\n\n\n\n<li><strong>Duration:<\/strong> 1\u20133 months (approx. 100 hours\/month)<\/li>\n\n\n\n<li><strong>Rok za prijavo:<\/strong> applications accepted on ongoing basis<\/li>\n\n\n\n<li><strong>Location:<\/strong> Jo\u017eef Stefan Institute (IJS), Jamova 39, Ljubljana, Slovenia<\/li>\n\n\n\n<li><strong>Contact:<\/strong> Prof. dr. Hana Ur\u0161i\u010d Nemev\u0161ek (Department K5), E-mail:\n<a href=\"mailto:Hana.ursic@ijs.si\" style=\"color:#0056B3;\" target=\"_blank\" rel=\"noopener\" title=\"mailto:Hana.ursic@ijs.si\">Hana.ursic@ijs.si<\/a><\/li>\n<\/ul>\n<\/div>\n\n\n\n<h4 class=\"wp-block-heading\"><\/h4>\n\n\n\n<h2 class=\"wp-block-heading has-text-color has-link-color wp-elements-2\" style=\"color:#004180\"><strong>ASIC Deaign and Verification<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Internship topics<\/strong>:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>ASIC design with open-source tools \u2013 tapeout possibility<\/li>\n\n\n\n<li>ASIC verification<\/li>\n<\/ol>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Provider:<\/strong> CC Chip.si in collaboration with JSI<\/li>\n\n\n\n<li><strong>Mentor:<\/strong> Jure Vre\u010da<\/li>\n\n\n\n<li><strong>Available positions:<\/strong> 3<\/li>\n\n\n\n<li><strong>Contact:<\/strong> Jure Vre\u010da, E-mail: <a href=\"mailto:jure.vreca@ijs.si\" style=\"color:#0056B3; target=\" _blank\"=\"\" rel=\"noopener\" title=\"mailto:jure.vreca@ijs.si\">jure.vreca@ijs.si<\/a><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h2 class=\"wp-block-heading has-text-color has-link-color wp-elements-3\" style=\"color:#004180\"><strong>Digital Circuit Design and Verification using SystemVerilog<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Internship topics<\/strong>:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>\nTraining in the use of tools for the development and verification of digital circuits in SystemVerilog for further development of the PulsePins control system.<br>\nProject link:<br>\n<a href=\"https:\/\/github.com\/rokzitko\/PulsePins\" style=\"color:#0056B3;\">https:\/\/github.com\/rokzitko\/PulsePins<\/a>\n<\/li>\n\n\n\n<li>Training in the use of tools for the development and verification of digital circuits in SystemVerilog for random number generators based on vacuum fluctuations and real-time entropy extraction.<br>Project link:<br><a href=\"https:\/\/github.com\/rokzitko\/toeplitz\" style=\"color:#0056B3;\">https:\/\/github.com\/rokzitko\/toeplitz<\/a><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Provider:<\/strong> CC Chip.si in collaboration with JSI<\/li>\n\n\n\n<li><strong>Mentor:<\/strong> Rok \u017ditko<\/li>\n\n\n\n<li><strong>Available positions:<\/strong> 3<\/li>\n\n\n\n<li><strong>Contact:<\/strong> Rok \u017ditko, E-mail: <a href=\"mailto:rok.zitko@ijs.si\" style=\"color:#0056B3; target=\" _blank\"=\"\" rel=\"noopener\" title=\"mailto:rok.zitko@ijs.si\">rok.zitko@ijs.si<\/a><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h2 class=\"wp-block-heading has-text-color has-link-color wp-elements-4\" style=\"color:#004180\"><strong>Silicon Devices Simulations using COMSOL<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Internship topics<\/strong>:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Different topics on simulations of silicon devices using COMSOL software<\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Provider:<\/strong> CC Chip.si in collaboration with JSI<\/li>\n\n\n\n<li><strong>Mentor:<\/strong> Uro\u0161 Cvelbar<\/li>\n\n\n\n<li><strong>Available positions:<\/strong> 1<\/li>\n\n\n\n<li><strong>Contact:<\/strong> Uro\u0161 Cvelbar, E-mail: <a href=\"mailto:uros.cvelbar@ijs.si\" style=\"color:#0056B3; target=\" _blank\"=\"\" rel=\"noopener\" title=\"mailto:uros.cvelbar@ijs.si\">uros.cvelbar@ijs.si<\/a><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h2 class=\"wp-block-heading has-text-color has-link-color wp-elements-5\" style=\"color:#004180\"><strong>Semiconductor Processing and Electronics Applications<\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Internship topics<\/strong>:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Ion implantation for chip production<\/li>\n\n\n\n<li>Electronics for space applications<\/li>\n\n\n\n<li>Electronics for nuclear applications<\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Mentor:<\/strong> \u017diga Bren\u010di\u010d<\/li>\n\n\n\n<li><strong>Available positions:<\/strong> 3<\/li>\n\n\n\n<li><strong>Internship duration:<\/strong> 1\u20133 months<\/li>\n\n\n\n<li><strong>Kontakt<\/strong>: \u017diga Bren\u010di\u010d, E-mail: <a href=\"mailto:ziga.brencic@ijs.si\" style=\"color:#0056B3; \" target=\"_blank\" rel=\"noopener\" title=\"mailto:ziga.brencic@ijs.si\">ziga.brencic@ijs.si<\/a><\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><\/h2>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Additional information<\/strong><\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Applications<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Applications are accepted on an ongoing basis.<br>Candidates should contact the mentor directly to discuss their background, interests, and internship availability.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>","protected":false},"excerpt":{"rendered":"<p>Available internships: Advanced materials and semiconductor-related technologies The Jo\u017eef Stefan Institute (Department K5) offers internship opportunities under the supervision of Prof. dr. Hana Ur\u0161i\u010d Nemev\u0161ek , focusing on advanced materials and semiconductor-related technologies. Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates. Internship topics: ASIC Deaign and Verification [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":35107,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,8],"tags":[12],"class_list":["post-35093","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-cc-chip-si-trainings","category-trainings","tag-active"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/comments?post=35093"}],"version-history":[{"count":5,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093\/revisions"}],"predecessor-version":[{"id":35648,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093\/revisions\/35648"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media\/35107"}],"wp:attachment":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media?parent=35093"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/categories?post=35093"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/tags?post=35093"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}