{"id":35093,"date":"2026-05-05T10:44:55","date_gmt":"2026-01-20T17:36:53","guid":{"rendered":"https:\/\/cc-chip.si\/?p=508"},"modified":"2026-05-18T14:26:02","modified_gmt":"2026-05-18T14:26:02","slug":"open-internship-positions-at-institut-jozef-stefan-ijs","status":"publish","type":"post","link":"https:\/\/cc-chip.si\/slo\/open-internship-positions-at-institut-jozef-stefan-ijs\/","title":{"rendered":"Open Internship positions at Institut “Jozef Stefan” (IJS)"},"content":{"rendered":"

About the internships<\/strong>:<\/p>\n\n\n\n

The Jo\u017eef Stefan Institute (Department K5) offers internship opportunities under the supervision of Prof. dr. Hana Ur\u0161i\u010d Nemev\u0161ek<\/a><\/strong>, focusing on advanced materials and semiconductor-related technologies.<\/p>\n\n\n\n

Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates.<\/p>\n\n\n\n

Internship topics<\/strong>:<\/p>\n\n\n\n

    \n
  1. Deposition and properties of electrodes on silicon substrates<\/li>\n\n\n\n
  2. Deposition and functional properties of various dielectric layers on
    silicon substrates<\/li>\n\n\n\n
  3. Study of topography and local functional properties layers on silicon substrates<\/li>\n\n\n\n
  4. Study of microstructure of functional layers on silicon substrates<\/li>\n\n\n\n
  5. Multilayer structures on silicon substrates<\/li>\n<\/ol>\n\n\n\n

    Kje:<\/strong><\/p>\n\n\n\n

    Jo\u017eef Stefan Institute (IJS), Jamova 39, Ljubljana, Slovenia<\/p>\n\n\n\n

    Duration:<\/strong> <\/p>\n\n\n\n

    1\u20133 months (approx. 100 hours\/month)<\/p>\n\n\n\n

    Rok za prijavo:<\/strong><\/p>\n\n\n\n

    applications accepted on ongoing basis<\/p>\n\n\n\n

    Contact:<\/strong><\/p>\n\n\n\n

    Prof. dr. Hana Ur\u0161i\u010d Nemev\u0161ek (Department K5)<\/p>\n\n\n\n

    E-mail: Hana.ursic@ijs.si<\/a><\/p>\n\n\n\n

    Additional internship opportunities at IJS<\/strong><\/h4>\n\n\n\n

    <\/p>\n\n\n\n

    ASIC Design and Verification<\/mark><\/strong><\/h5>\n\n\n\n

    Mentor:<\/strong> Jure Vre\u010da
    Available positions:<\/strong> 3<\/p>\n\n\n\n

      \n
    1. ASIC design with open-source tools \u2013 tapeout possibility<\/li>\n\n\n\n
    2. ASIC verification<\/li>\n<\/ol>\n\n\n\n

      Contact:<\/strong>
      Jure Vre\u010da <\/p>\n\n\n\n

      E-mail: jure.vreca@ijs.si<\/a><\/p>\n\n\n\n

      <\/p>\n\n\n\n

      Digital Circuit Design and Verification using SystemVerilog<\/mark><\/strong><\/h5>\n\n\n\n

      Mentor:<\/strong> Rok \u017ditko
      Available positions:<\/strong> 3<\/p>\n\n\n\n

        \n
      1. Training in the use of tools for the development and verification of digital circuits in SystemVerilog for further development of the PulsePins control system.
        Project link:
        https:\/\/github.com\/rokzitko\/PulsePins<\/a><\/li>\n\n\n\n
      2. Training in the use of tools for the development and verification of digital circuits in SystemVerilog for random number generators based on vacuum fluctuations and real-time entropy extraction.
        Project link:
        https:\/\/github.com\/rokzitko\/toeplitz<\/a><\/li>\n<\/ol>\n\n\n\n

        Contact:<\/strong>
        Rok \u017ditko <\/p>\n\n\n\n

        E-mail: rok.zitko@ijs.si<\/a><\/p>\n\n\n\n

        <\/p>\n\n\n\n

        Silicon Device Simulations using COMSOL<\/mark><\/strong><\/h5>\n\n\n\n

        Mentor:<\/strong> Uro\u0161 Cvelbar
        Available positions:<\/strong> 1<\/p>\n\n\n\n

          \n
        1. Different topics on simulations of silicon devices using COMSOL software<\/li>\n<\/ol>\n\n\n\n

          Contact:<\/strong>
          Uro\u0161 Cvelbar <\/p>\n\n\n\n

          E-mail: uros.cvelbar@ijs.si<\/a><\/p>\n\n\n\n

          <\/p>\n\n\n\n

          Semiconductor Processing and Electronics Applications<\/mark><\/strong><\/h5>\n\n\n\n

          Mentor:<\/strong> \u017diga Bren\u010di\u010d
          Available positions:<\/strong> 3
          Internship duration:<\/strong> 1\u20133 months<\/p>\n\n\n\n

            \n
          1. Ion implantation for chip production<\/li>\n\n\n\n
          2. Electronics for space applications<\/li>\n\n\n\n
          3. Electronics for nuclear applications<\/li>\n<\/ol>\n\n\n\n

            Contact:<\/strong>
            \u017diga Bren\u010di\u010d <\/p>\n\n\n\n

            E-mail: ziga.brencic@ijs.si<\/a><\/p>\n\n\n\n

            <\/p>\n\n\n\n

            Applications<\/h4>\n\n\n\n

            Applications are accepted on an ongoing basis.
            Candidates should contact the mentor directly to discuss their background, interests, and internship availability.<\/p>\n\n\n\n

            <\/p>","protected":false},"excerpt":{"rendered":"

            About the internships: The Jo\u017eef Stefan Institute (Department K5) offers internship opportunities under the supervision of Prof. dr. Hana Ur\u0161i\u010d Nemev\u0161ek, focusing on advanced materials and semiconductor-related technologies. Internships provide hands-on experience in the preparation, characterization, and analysis of functional layers on silicon substrates. Internship topics: Where: Jo\u017eef Stefan Institute (IJS), Jamova 39, Ljubljana, Slovenia […]<\/p>\n","protected":false},"author":1,"featured_media":35107,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,8],"tags":[12],"class_list":["post-35093","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-cc-chip-si-trainings","category-trainings","tag-active"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/comments?post=35093"}],"version-history":[{"count":5,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093\/revisions"}],"predecessor-version":[{"id":35278,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/posts\/35093\/revisions\/35278"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media\/35107"}],"wp:attachment":[{"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/media?parent=35093"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/categories?post=35093"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cc-chip.si\/slo\/wp-json\/wp\/v2\/tags?post=35093"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}